Silicon Labs /Series1 /EFR32MG1B /EFR32MG1B231F256GM48 /PCNT0 /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)MODE0 (FILT)FILT 0 (RSTEN)RSTEN 0 (CNTRSTEN)CNTRSTEN 0 (AUXCNTRSTEN)AUXCNTRSTEN 0 (DEBUGHALT)DEBUGHALT 0 (HYST)HYST 0 (S1CDIR)S1CDIR 0 (BOTH)CNTEV 0 (NONE)AUXCNTEV 0 (CNTDIR)CNTDIR 0 (EDGE)EDGE 0 (DISABLED)TCCMODE 0 (DIV1)TCCPRESC 0 (LTOE)TCCCOMP 0 (PRSGATEEN)PRSGATEEN 0 (TCCPRSPOL)TCCPRSPOL 0 (PRSCH0)TCCPRSSEL 0 (TOPBHFSEL)TOPBHFSEL

CNTEV=BOTH, TCCMODE=DISABLED, AUXCNTEV=NONE, MODE=DISABLE, TCCCOMP=LTOE, TCCPRSSEL=PRSCH0, TCCPRESC=DIV1

Description

Control Register

Fields

MODE

Mode Select

0 (DISABLE): The module is disabled.

1 (OVSSINGLE): Single input LFACLK oversampling mode (available in EM0-EM3).

2 (EXTCLKSINGLE): Externally clocked single input counter mode (available in EM0-EM3).

3 (EXTCLKQUAD): Externally clocked quadrature decoder mode (available in EM0-EM3).

4 (OVSQUAD1X): LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM3).

5 (OVSQUAD2X): LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM3).

6 (OVSQUAD4X): LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM3).

FILT

Enable Digital Pulse Width Filter

RSTEN

Enable PCNT Clock Domain Reset

CNTRSTEN

Enable CNT Reset

AUXCNTRSTEN

Enable AUXCNT Reset

DEBUGHALT

Debug Mode Halt Enable

HYST

Enable Hysteresis

S1CDIR

Count Direction Determined By S1

CNTEV

Controls When the Counter Counts

0 (BOTH): Counts up on up-count and down on down-count events.

1 (UP): Only counts up on up-count events.

2 (DOWN): Only counts down on down-count events.

3 (NONE): Never counts.

AUXCNTEV

Controls When the Auxiliary Counter Counts

0 (NONE): Never counts.

1 (UP): Counts up on up-count events.

2 (DOWN): Counts up on down-count events.

3 (BOTH): Counts up on both up-count and down-count events.

CNTDIR

Non-Quadrature Mode Counter Direction Control

EDGE

Edge Select

TCCMODE

Sets the Mode for Triggered Compare and Clear

0 (DISABLED): Triggered compare and clear not enabled.

1 (LFA): Compare and clear performed on each (optionally prescaled) LFA clock cycle.

2 (PRS): Compare and clear performed on positive PRS edges.

TCCPRESC

Set the LFA Prescaler for Triggered Compare and Clear

0 (DIV1): Compare and clear event each LFA cycle.

1 (DIV2): Compare and clear performed on every other LFA cycle.

2 (DIV4): Compare and clear performed on every 4th LFA cycle.

3 (DIV8): Compare and clear performed on every 8th LFA cycle.

TCCCOMP

Triggered Compare and Clear Compare Mode

0 (LTOE): Compare match if PCNT_CNT is less than, or equal to PCNT_TOP.

1 (GTOE): Compare match if PCNT_CNT is greater than or equal to PCNT_TOP.

2 (RANGE): Compare match if PCNT_CNT is less than, or equal to PCNT_TOP[15:8]], and greater than, or equal to PCNT_TOP[7:0].

PRSGATEEN

PRS Gate Enable

TCCPRSPOL

TCC PRS Polarity Select

TCCPRSSEL

TCC PRS Channel Select

0 (PRSCH0): PRS Channel 0 selected.

1 (PRSCH1): PRS Channel 1 selected.

2 (PRSCH2): PRS Channel 2 selected.

3 (PRSCH3): PRS Channel 3 selected.

4 (PRSCH4): PRS Channel 4 selected.

5 (PRSCH5): PRS Channel 5 selected.

6 (PRSCH6): PRS Channel 6 selected.

7 (PRSCH7): PRS Channel 7 selected.

8 (PRSCH8): PRS Channel 8 selected.

9 (PRSCH9): PRS Channel 9 selected.

10 (PRSCH10): PRS Channel 10 selected.

11 (PRSCH11): PRS Channel 11 selected.

TOPBHFSEL

TOPB High Frequency Value Select

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